Petri net to PLC
converting:
Inputs and Outputs
mapping
2017, 2018, 2019, José Gaspar
Introduction
Designing Petri nets with input/output (I/O) is a way of designing programs for PLCs. A Petri net with I/O interacts with a system or, in other words, supervises a system. A Petri net typically has inputs at the transitions and outputs at the places. See in figure1 the arrows "PN actuation" meaning the outputs required to drive the system, and see "PN inputs" meaning the signals observed in the system and used to drive the Petri net.
Figure1: Petri net supervising the system "HW to be controlled".
In this page is described how to convert to PLC code, namely structured text, a Petri net represented by its incidence matrix, D, and having inputs / outputs associated to transitions and places, respectively. The matrix D has size n lines by m columns, where n denotes the number of places and m denotes the number of transitions. Matrix D=D+-D-. In code, the D+ and D- matrices are usually denoted as Pre= D- and Pos= D+. The initial marking is denoted as mu0.
In the following is presented (i) the top level function converting PN to PLC code, (ii) a specification for encoding PLC hardware inputs to Petri net transitions, and (iii) a specification for encoding Petri net places to PLC hardware outputs.
Convert PN to PLC code
In the end one desires to obtain Structured Text code for a PLC. Converting a Petri net to PLC code starts by defining a Petri net as a structure containing the incidence matrix decomposed as Pre and Pos, and containing the initial state mu0.
See next an example of a Petri net defined as a structure PN:
function PN= define_petri_net
% Define the Petri Net
%
write incidence matrix
D by columns (and transpose it)
%
get "pre"
(D-) from negative entries of D
%
get "pos"
(D+) from positive entries of D
%
define initial marking
"mu0"
%
D=[ -1 0 1
-1 1
1
-1 0 0
0
0
1 -1 0
0
0
0 0 1
-1 ];
pre= -D.*(D<0);
pos= D.*(D>0);
mu0= [1 0 0 0]';
% define priority transitions (empty indicates no specific
priorities)
tprio= [4];
% 0.5 seconds timeout from places p1, p2 and p3 to
transitions t1 t2 t3
T= 0.5;
ttimed= [T 1 1; T 2 2; T 3 3]; %
column2=place, column3=transition
% output structure
PN= struct('pre',pre, 'pos',pos,
'mu0',mu0,
'tprio',tprio, 'ttimed',ttimed);
Note that the Petri net can also have timed transitions and transitions which have priority of firing with respect to the other transitions of the model.
Given the Petri net and the inputs /
outputs (whose specifications are detailed in the next sections), the Structure
Text is created by the main compiling function plc_make_program.m
function plc_make_program(ofname, PN, input_map, output_map, show_places)
%
% Write to file a PLC program (structured text) given a Petri net (PN),
% and given the input/output physical mappings. May also add a list of
% places (only one active at each moment), to be shown as PLC outputs.
This main function, that creates the
Structured Text, handles the inputs and outputs by calling auxiliary functions
converting (i) logic functions of input signals into
transitions and (ii) places to signals, as detailed in the next sections.
Inputs Mapping
An example of inputs mapping is the
following:
function inp_map= define_input_mapping
inp_map= { ...
0, 4 ; ... % input0 fires transition4
-(0+100), 5 ; ... % negated input0 fires t5
};
In this example one has the input bit
number 0 firing transitions numbers 4 and 5. In the first case the input bit is
used directly, while in the second case its negated logic value is used
instead. Notice that negating the input is represented by adding 100 to the
number of the bit, and prefixing the result with a minus sign.
The inputs specification is used by the
main compiling function plc_make_program.m which calls the auxiliary function plc_map_inputs.m :
function prg_tfire = plc_map_inputs( inp_bits_lst, trans_lst, options )
%
% inp_bits_lst : 1xN : PLC input module list of bits
% trans_lst : 1xN : Petri net transitions list (indexes, not strings)
%
% prg_tfire : list of strings : lines of structured text
This function is called once per line of the Nx2 list inp_map previously introduced. The general description of the inp_map is that the first column contains physical inputs specification while the second column contains an identification of the Petri net transition. In the following are various examples of specifications of input mappings.
Example I.1, one input to one transition:
inp_map= { 15, 25 }; % map input 15 (e.g.
%i0.3.15) to transition t25
Example I.2, AND of two inputs to one transition:
inp_map= { [0 4]', 4 }; % input 0 AND input 4 ->
transition 4
Example I.3, ANDs of pairs of inputs to transitions:
inp_map= { [1 2 3; 4 4 4], [5 6 3] };
%
i1 & i4 -> trans5
% i2 &
i4 -> trans6
% i3 &
i4 -> trans3
Example I.4, negating entries of some inputs:
inp_map= { [-100 -101 -102 -103; 4 4 4 4], [9 10 7 8] };
% NOT(i0)&i4 -> trans9
% NOT(i1)&i4 -> trans10
% NOT(i2)&i4 -> trans7
% NOT(i3)&i4 -> trans8
Example I.5, "OR of ANDs", each pair of inputs is "ANDed" and all pairs are combined by a "OR":
mylst= {{[0 1], [0 2], [0 3], [1 2], [1 3], [2 3]}};
inp_map= { struct('op', 'OR_of_ANDs', 'transId',28, 'lst',mylst), []};
% (
i0&i1 OR i0&i2 OR i0&i3 OR i1&i2 OR i1&i3 OR i2&i3 )
=> trans28
In other words, transition 28 receives the OR of multiple ANDs.
Example I.6, NOR of ANDs, just an extra NOT(.) to the previous case:
mylst= {{[0 1], [0 2], [0 3], [1 2], [1 3], [2 3]}};
inp_map= { struct('op', 'NOR_of_ANDs', 'transId',28, 'lst',mylst), []};
%
NOT( i0&i1 OR i0&i2 OR i0&i3 OR i1&i2 OR i1&i3 OR i2&i3
) => trans28
In this case transition 28 receives the negation of a multi-entry OR. Each entry of the OR is a AND.
Outputs Mapping
The outputs mapping allow copying from the Petri net state of places to real PLC hardware outputs.
Example Q.1, three places mapped one by one to one output bit:
function output_map= define_output_mapping
% map PN places 1..3 to the first output
bits
zCode= plc_z_code_helper('config_get');
output_map= { ...
1,
zCode.outpMin+0 ; ...
2,
zCode.outpMin+1 ; ...
3,
zCode.outpMin+2 ;
};
The field outpMin indicates that the PLC output names depend on the installed modules. For example one may have as a first output bit %q0.4.0 or %q0.3.16, depending on whether the installed output module is “DSY16T2” or "TSX DMY 28FK".
Example Q.2, multiple places light one single output bit. As compared to the previous example, the first output bit is not used i.e. outputs start at zCode.outpMin+1, and the places 1 OR 3 both report to the output bit zCode.outpMin+2.
output_map= { ...
2, zCode.outpMin+1
; ...
[1 3],
zCode.outpMin+2 ;
4, zCode.outpMin+3 ; ...
};
Download and Usage
Download the zip file pn_to_plc_v3.zip and decompress it to a folder of your choice.
To run the main demo:
>> cd tst1_blink_turn_on_off
>> tst1_blink_on_off
Maintenance
This program was created for the purpose of helping classes. There is no continuous maintenance other the requirements associated to the classes.
This program is distributed in the hope that it will be useful, but without any warranty; without even the implied warranty of merchantability or fitness for a particular purpose.
Acknowledgment
In case you find this software useful and do any publication in the sequel please refer to the course Industrial Automation.
Contact
|
Prof. José Gaspar Instituto de Sistemas e Robótica, Instituto Superior Técnico, Torre Norte Av. Rovisco Pais, 1 1049-001 |
Office: Torre Norte do IST, 7.19 |